refactor: heel_f64x8 uses crate::simd::F64x8 polyfill, add SIMD cosine Replace raw std::arch intrinsics with crate::simd::F64x8 polyfill. Automatic dispatch: AVX-512 (native __m512d) → AVX2 (2×__m256d) → scalar. Consumer writes crate::simd::F64x8 — polyfill handles tier selection. Added SIMD cosine kernels using F64x8 FMA: cosine_f64_simd() — single-pass dot + norm_a + norm_b via F64x8 cosine_f32_to_f64_simd() — f32 input, f64 precision cosine dot_f64_simd() — F64x8 FMA dot product on f64 slices sum_sq_f64_simd() — F64x8 sum of squares 12 tests passing (6 HEEL + 6 cosine). https://claude.ai/code/session_01ChLvBfpJS8dQhHxRD4pYNp#75
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Consumers (bgz-tensor) need read access to Welford σ tracking state for quarter-sigma band computation. Fields remain private; accessors provide read-only access. https://claude.ai/code/session_01ChLvBfpJS8dQhHxRD4pYNp
8 HEEL planes × 1 distance each = 8 f64 = one F64x8 register. LazyLock dispatch: AVX-512 (vmulpd + vreducepd) → AVX2 (2×vmulpd) → scalar. Functions: heel_weighted_distance(&[f64;8], &[f64;8]) → f64 (weighted dot) heel_plane_distances(&[u64;8], &[u64;8]) → [f64;8] (Hamming per plane) heel_weighted_hamming(a, b, weights) → f64 (full pipeline) Predefined weights: UNIFORM_WEIGHTS = [1.0; 8] HEEL_7PLUS1_WEIGHTS = [1,1,1,1,1,1,1, 0.5] (contradiction at half) 6 tests passing. https://claude.ai/code/session_01ChLvBfpJS8dQhHxRD4pYNp
Replace raw std::arch intrinsics with crate::simd::F64x8 polyfill. Automatic dispatch: AVX-512 (native __m512d) → AVX2 (2×__m256d) → scalar. Consumer writes crate::simd::F64x8 — polyfill handles tier selection. Added SIMD cosine kernels using F64x8 FMA: cosine_f64_simd() — single-pass dot + norm_a + norm_b via F64x8 cosine_f32_to_f64_simd() — f32 input, f64 precision cosine dot_f64_simd() — F64x8 FMA dot product on f64 slices sum_sq_f64_simd() — F64x8 sum of squares 12 tests passing (6 HEEL + 6 cosine). https://claude.ai/code/session_01ChLvBfpJS8dQhHxRD4pYNp
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